1. Field of the Invention
The present invention relates to a switching power supply apparatus of a synchronous rectification type.
2. Description of the Related Art
An example of a switching power supply of a synchronous rectification type according to a related art is to configure a circuit using a comparator as illustrated in FIG. 6. For example, Japanese Patent Laid-Open No. 07-007928 discloses a circuit configured such that a comparator detects a voltage across a synchronous rectification FET and drives the synchronous rectification FET. In FIG. 6, 1001 denotes a transformer, 1002 denotes a DC power supply, 1003 denotes a primary-side MOSFET (hereafter, referred to as a primary-side FET), 1004 denotes a secondary-side electrolytic capacitor, 1005 denotes a load, 1006 denotes a switching control circuit, 1007 denotes a synchronous rectification FET, and 1008 denotes a comparator. When the primary-side FET 1003 turns on, energy is stored in the transformer. Thereafter, if the primary-side FET 1003 turns off, a source voltage of the synchronous rectification FET 1007 rises, and a “+” terminal voltage of the comparator 1008 becomes higher than a “−” terminal voltage. As a result, the synchronous rectification FET 1007 turns on, and a current starts to flow. Thereafter, when the current becomes 0 A and a current starts flowing reversely from the positive input terminal of the capacitor 1004 to the transformer 1001, the negative input terminal voltage of the synchronous rectification FET 1007 becomes higher than the “+” input terminal voltage, and the gate voltage of the synchronous rectification FET 1007 falls down. As a result, the synchronous rectification FET 1007 turns off. Thus, it is possible to control the synchronous rectification FET by the circuit including a small number of components configured in the above-described manner. In the circuit described above, the comparator may be replaced with a circuit including a PNP transistor and a NPN transistor as illustrated in FIG. 7. In the circuit illustrated in FIG. 7, the synchronous rectification FET is replaced with a PNP transistor.
Instead of directly detecting a current, a circuit may be configured based on an ET product of a transformer as disclosed, for example, in Japanese Patent No. 4126558 or Japanese Patent No. 4158054. FIG. 8 illustrates a circuit configuration disclosed in Japanese Patent No. 4126558. In FIG. 8, 1201 denotes a transformer, 1202 denotes a power supply, 1203 denotes a primary-side FET, 1204 denotes a synchronous rectification FET, 1205 denotes a secondary-side electrolytic capacitor, 1206 denotes a load, 1207 denotes a first constant current source, 1208 denotes a capacitor, 1209 denotes a second constant current source, 1210 denotes a reference voltage, 1211 denotes a comparator, and 1212 and 1213 respectively denote resistors. The constant current source 1207 is configured to generate a current proportional to a voltage of the transformer 1201 during a period in which the primary-side FET 1203 is in an on state. During the period in which the primary-side FET 1203 is in the on state, the voltage-time product in terms of the voltage appearing on the transformer 1201 is stored as a voltage across the capacitor. The second current source 1209 is configured to generate a current proportional to a voltage of the transformer 1201 during a period in which the primary-side FET 1203 is in an off state. When the primary-side FET 1203 turns off, the switch turns on and the voltage stored in the capacitor 1208 is discharged. When the voltage across the capacitor 1208 falls down to a value determined by the reference voltage 1210, the comparator 1211 operates. In response, a logic circuit inverts and the synchronous rectification FET 1204 turns off. FIG. 9 illustrates a circuit configuration disclosed in Japanese Patent No. 4158054, which is a simplified version of the circuit illustrated in FIG. 8. In this circuit configuration, the constant current sources are replaced with resistors such that the circuit operates in a similar manner to that disclosed in Japanese Patent No. 4126558.
Other known circuit configurations include a configuration in which a reference voltage source is connected in series to an input terminal of a comparator, a configuration in which a plurality of reference voltages serving as threshold values are disposed thereby to provide a hysteresis in characteristic, and a configuration in which a switchover of a current flowing from a current source is detected.
However, in the circuit configuration disclosed in Japanese Patent Laid-Open No. 07-007928, if the synchronous rectification FET has a small on-resistance and a drain-source voltage thereof is small, the circuit does not operate correctly.
In particular, when the switching power supply operates with a low load as in a critical mode or a discontinuous mode, the current flowing through the synchronous rectification FET on the secondary side of the transformer falls down to a value nearly equal to 0 A (ampere) and the drain-source voltage of the synchronous rectification FET becomes low. Therefore, if the synchronous rectification FET used has a low on-resistance, it is difficult to achieve a correct operation.
The above problem may be avoided by employing a synchronous rectification FET with a high on-resistance. However, such a synchronous rectification FET with a high on-resistance does not provide a high efficiency in the synchronous rectification operation. Besides, a synchronous rectification FET with a low on-resistance is low in cost, which provides an advantage that the circuit is produced at low cost. The recent tendency is to increase the operation efficiency of the power supply and reduce the cost by further reducing the on-resistance of the synchronous rectification FET. This means that the problem described above will become more serious.
On the other hand, in the circuit configurations disclosed in Japanese Patent No. 4126558 and Japanese Patent No. 4158054, the current is not directly detected and thus the operation reliability does not depend on the on-resistance of the synchronous rectification FET. Furthermore, because the circuit is based on the integral operation, the circuit is substantially free of operation errors and the circuit is simple in configuration. However, on the other hand, it is necessary to make setting and adjustment of the threshold value such that the synchronous rectification FET turns off when the current becomes 0 A. However, in a case where a large change occurs in output voltage which may occur, for example, in a short period immediately after the operation is started, or in a case where a large change occurs in load, the average time of charging and discharging the capacitor varies, and thus a shift occurs between the 0-current timing and the turning-off timing of the synchronous rectification FET.
This problem in the circuit configurations disclosed in Japanese Patent No. 4126558 and Japanese Patent No. 4158054 is caused by the fact that the operation of the synchronous rectification FET is controlled not based on the direct detection of the current but based on prediction and thus it is necessary for the operation timing to have a margin, i.e., it is necessary to turn off the synchronous rectification FET slightly earlier. That is, in the operation with such a margin, the synchronous rectification FET needs a longer period in which the body diode is in the on state, which results in a reduction in operation efficiency.
Furthermore, a forward voltage of the body diode appears during the on-period of the synchronous rectification FET. The forward voltage is much greater than the voltage detected when the current is 0 A. Therefore, in the circuit configuration in which the voltage across the synchronous rectification FET is detected using the comparator, the synchronous rectification FET is turned off before the current becomes 0 A, which may result in an operation error.
In view of the above, the present invention provides a switching power supply of a synchronous rectification type capable of operating correctly using a switching element with a low on-resistance without resulting in a reduction in efficiency.